In recent years, great efforts have been made to bring a new non-volatile memory technology based on magnetoresistive random access memory cells into commercial use. For further explaining a typical MRAM cell structure, reference is now made to FIG. 1.
A magnetoresistive memory cell includes a layered structure of ferromagnetic layers 1, 2 separated by a non-magnetic tunneling barrier 3 and arranged into a magnetic tunnel junction (MTJ). More specifically, magnetization of one ferromagnetic layer 2 (“reference layer”) is magnetically fixed or pinned, while magnetization of the other ferromagnetic layer 1 (“free layer”) is free to be switched between two preferred directions given by the same and opposite directions with respect to the fixed magnetization of the reference layer. Depending upon the magnetic states of the free layer 1, i.e. parallel or antiparallel states of its magnetization with respect to the magnetization of the reference layer 2, the magnetic memory cell exhibits two different resistance values R1, R2 in response to a voltage applied across the magnetic tunnel junction barrier. Thus, particular resistance of the memory cell reflects the magnetization states of the free layer, wherein resistance is low when the magnetization is parallel and high when the magnetization is antiparallel (R1<R2). Hence, detection of resistance values allows to provide a logic zero (“logic low”) or a logic one (“logic high”) state information stored in the magnetic memory cell.
Conventionally, an MRAM cell is written to through the application of magnetic fields created by bidirectional currents (IWWL, IBL) flowing through dedicated current lines, typically bit lines (BL) and write word lines (WWL) crossing at right angles with the memory cells each being positioned at an intersection thereof. If a magnetic field in the direction opposite to the magnetization direction of the free layer is applied, then the magnetic moment vector of the free layer is reversed in case a critical magnetic field value is reached, which is also referred to as reversal magnetic field. Assuming that a magnetic field applied to the direction of the magnetization hard axis is represented by Hy and a magnetic field applied to the direction of the easy axis thereof is represented by Hx, then a relationship Hx(2/3)+Hy(2/3)=Hc(2/3) is established, where Hc represents the anisotropic magnetic field of the free layer. Since this curve forms an astroid on a Hx-Hy-plane, it is called astroid curve. As can be seen from above relationship, a composite synthetic magnetic field enables the selection of a single MRAM cell in case the sum of both magnetic fields at least amounts to the reversal magnetic field. Based upon the above, the well-known “Stoner-Wohlfahrt”-switching scenario is typically used for switching MRAM-cells.
For the design of fast MRAM memories, each MTJ typically is combined with one select transistor ST in a single ended configuration, as shown in FIG. 2. At writing, current is applied to the bit line BL and the write word line WWL to generate a synthetic magnetic field at a cell position of interest so as to control the direction of magnetization of the free layer in the MTJ. At reading, voltage is applied to read word line RWL to render select transistor ST conductive. Current is then provided from bit line BL to the current sink GND via the MTJ and a conductive path that is comprised of plural conductive structures (MX, VX, . . . ) and select transistor ST. Here, the magnitude of the flowing current varies depending on the direction of the free layer magnetization with respect to the reference layer magnetization.
Reference is now made to FIG. 3 for further explaining read operation of memory cells in a basic 1-Transistor-1-MTJ-(1T1MTJ) configuration of memory cells in a typical array of MRAM cells. In such memory cell array having a plurality of bit lines and a plurality of word lines crossing in right angles, in single ended configurations, a plurality of memory cell columns are formed. In each of such memory cell columns, a bit line connects a memory cell and a select transistor, as exemplified by memory cell 4 being series connected to select transistor ST via bit line BL. More specifically, a first end of each of the memory cells is connected to the BL and a second end thereof is connected to the current path of the select transistor ST which may be rendered conductive applying voltage to the read word line RWL connected to the control gate thereof.
In such array of memory cells, apart from the memory cell columns, reference cell columns are provided comprising reference cells that are physically identical to the memory cells and are arranged in a same single ended configuration to form cell columns such as the memory cells but are not intended for user programming but for holding logic values to provide a reference current (“dummy cells”). Memory cells and reference cells the control gates of select transistors of which are connected by a single word line (RWL) form a sub-array of the MRAM array.
Further, cell column selector 5 is used to connect both reference cell columns and to select and connect each of the memory cell columns to a differential sense amplifier (SA) 6 having three different inputs, one for each of the memory cell columns and two for both reference cell columns. Differential sense amplifier 6 comprising comparator 7 is for sensing of logic states that is to say resistivity values of the cells connected therewith, wherein each of the selected memory cell columns as well as reference cell columns typically is kept at a constant potential by means of bit line clamping transistors 9. For sensing of resistivity values of the memory cells, bit line clamping transistor 9 that may be connected to each of the memory cells is connected to one input (e.g. “+”—input) of comparator 7 with both reference cell columns comprising reference cells (“ref. cell 1” and “ref. cell 0” in FIG. 3) that are coupled in parallel being connected to another input (e.g. “−”—input) of comparator 7. Furthermore, two load devices 8 are provided, one of which being series connected to the current path of the bit line clamping transistor that may be series connected to each of the memory cells, while the other one being series connected to the current path of the parallely coupled bit line clamping transistors of the reference cells. More particularly, being kept at a constant potential by means of bit line clamping transistors 9, current of the cell columns flows through load devices 8 to create a potential value on the inputs of comparator 7.
In order to be used as reference cell, as is conventional, one of the reference cells has to be programmed to a logic high state such as a logic one state and the other reference cell has to be programmed to a logic low state such as a logic zero state. Thus, due to parallel coupling of the reference columns, an averaged signal of the logic values “high” and “low” can be obtained at the “−”—input of the sense amplifier to be used as reference signal. This allows to determine resistivity values that is to say logic values of the selected memory cells comparing signals of both inputs of the comparator 7, the result of which comparison is given at output (out) of the sense amplifier 6.
Accordingly, as above-outlined, for determining logic states of the selected memory cells, reference cells have to be programmed in a way that one cell is in a state representing a logic high value while the other cell is in a state representing a logic low value to thereby obtain an averaged reference signal. This has to be done for every pair of reference cells for each RWL of every sub-array of the MRAM array as above-described in structural aspects.
Usually programming of reference cells into defined logic states is not a problem as the state of a reference cell is exactly defined by the WWL and BL programming currents. Even if the initial state of the reference cell is not known, applying the WWL and BL currents with the right current directions will result in the desired logic high or low states of the targeted reference cell.
However, this situation is not true in a memory array based on rotational switching memory cells (“toggle cells”), that have been proposed as a new concept of memory cells in recent years. More specifically, in any rotational switching cell, the free layer is designed to be a layered stack of ferromagnetic free layers that are antiferromagnetically coupled with each other, where the number of antiferromagnetically coupled layers may be appropriately chosen to increase the effective magnetic switching volume of the MRAM device. See, for example, U.S. Pat. No. 6,531,723 B1 to Engel et al., the disclosure of which is incorporated herein by reference.
For the switching of such memory cells another switching scenario, the so-called “adiabatic rotational (toggle) switching” (see for instance U.S. Pat. No. 6,545,906 B1 to Savtchenko et al.) typically is used. In short, adiabatic rotational switching relies on the “spin-flop” phenomenon, which lowers the total magnetic energy in an applied magnetic field by rotating the magnetic moment vectors of the antiferromagnetically coupled ferromagnetic free layers. More specifically, assuming that a bit line magnetic field HBL and a write word line magnetic field HWWL respectively arrive at the MRAM cell for its switching, and that antiferromagnetically coupled magnetic moment vectors M1 and M2 exhibited by the ferromagnetic free layers are inclined at a 45° angle to the word and bit lines, respectively, a timed switching pulse sequence of applied magnetic fields in a typical “toggling write” mode is at follows: at a time t0 neither a write word line current nor a bit line current are applied resulting in a zero magnetic field H0 of both HBL and HHWL. At a time t1, the write word line current is increased to H1 and magnetic moment vectors M1 and M2 begin to rotate either clockwise or counter-clockwise, depending on the direction of the write word line current. At a time t2, the bit line current is switched on, where it is chosen to flow in a certain direction so that both magnetic moment vectors M1 and M2 are further rotated in the same clockwise or counter-clockwise direction as the rotation caused by the word line magnetic field. At this time t2, both the word and bit line currents are on, resulting in magnetic field H2 with magnetic moment vectors M1 and M2 being nominally orthogonal to the net magnetic field direction, which is 45° with respect to the current lines. At a time t3, the word line current is switched off, resulting in magnetic field H3, so that magnetic moment vectors M1 and M2 are being rotated only by the bit line magnetic field. At this point of time, magnetic moment vectors M1 and M2 have generally been rotated past their hard axis instability points. Finally, at a time t4, the bit line current is switched off, again resulting in zero magnetic field H0, and magnetic moment vectors M1 and M2 will align along the preferred anisotropy axis (easy axis) in a 180° angle rotated state as compared to the initial state.
Accordingly, with regard to the magnetic moment vector of the reference layer, the MRAM cell has been switched from its parallel state into its anti-parallel state, or vice versa, depending on the state switching (“toggling”) starts off with.
Accordingly, applying WWL and BL programming currents to rotational switching cells, only toggling of the cell can be achieved. This is not a problem for the regular memory cells as their programming state can be determined by the sense amplifier of the memory chip. The cell can then be toggled or left unchanged depending on the desired programming state.
However, for the sense amplifier being able to read the actual state of the cell, preprogrammed reference cells are usually necessary. Hence, for the reference cells a problem occurs that their state has to be determined before they can be programmed into the desired state.
Basically, the state of the reference cells could be determined using a self-referencing sensing scheme. However, implementing a self-referencing sensing scheme into a high-speed sense amplifier is critical concerning performance and chip area.